Conventional tools for designing integrated circuits use specific grids when laying out the components in a design. For example, some older grids use 100 nm unit spacing, while newer grids use 5 nm and 1 nm spacings. Grids include rigid rules regarding where structures can be placed. For example, when using a 5 nm grid, lines and points can only be placed every 5 nm. Thus, using a finer grid can offer a designer flexibility in placement of structures. However, the tradeoff of flexibility is data volume, which increases significantly as a grid becomes finer. Furthermore, in some scenarios, it is undesirable to use differently sized grids (e.g., a 5 nm grid and a 1 nm grid) for components that are placed together in the same device (e.g., a word line driver and a memory array placed together in a memory circuit) because unexpected sizing issues may occur at the boundary of the two components.
FIG. 1 shows an example design 100 using a conventional approach and a 5 nm grid. The design 100 has a gate 101 with a 35 nm gate length, a gate 102, and a contact 103. The gate pitch is 135 nm, and the length of the space between the gates 101 and 102 is 100 nm. The contact 103 is placed 30 nm from each gate 101 and 102, which conforms with the 5 nm grid, is physically symmetrical and thus results in overall symmetrical behavior.
Some high-performance circuits such as word line drivers use a gate with a 30 nm gate length, which when applied to the design 100, makes significant changes if the gate pitch is to be preserved. Typically, the gate pitch in word line drivers is preferred to match with the word line pitch in the memory array. For example, the distance between gates 101 and 102 increases from 100 nm to 105 nm. To achieve symmetrical behavior, the midpoint between the two gates 101 and 102, which is 52.5 nm is where the contacts would be conventionally positioned. Such a location, however, does not conform to a 5 nm manufacturing grid, nor even to a 1 nm grid. Currently, there is no technique available to reposition the circuit structures in the design 100 to accommodate a 30 nm gate length without switching to a finer grid and obtaining waivers of design rules.